People

Phil Kuekes

E-mail: philip.kuekes@hp.com

Location:
Quantum Structures Research Initiative Department
Hewlett-Packard Laboratories
Palo Alto, California

Biography:
Philip J. Kuekes is a member of the technical staff at Hewlett-Packard Laboratories in Palo Alto, California. He got his BS in Physics from Yale University in1969. He was co-designer of the first commercial array processor at Raytheon Computer (1970-71). This machine, the first low cost implementation of the newly discovered (1965) Fast Fourier Transform, was used extensively for seismic exploration in the 1970s.

He was Project Engineer at Ling Electronics (1972-74) responsible for designing the Ling Array Processor, a state of the art array processor used by the Naval Research Laboratories for acoustic vibration testing of satellites. He formed a consulting business, Kuekes Engineering (1975-1979), to design hardware and microcode for highly pipelined systems.

Clients included: NCR Corporation, Ling Electronics, and the National Severe Storms Center.

The machine he designed for the National Severe Storms Center enabled the first digital Doppler radar for tornado detection. At ESL, Inc. (1980-90) he created a number of highly parallel special purpose computers. He published an algorithm in 1981 on Fast Sparse Matrix Computations, with R. Schreiber which was one of the first papers to propose static scheduling to dramatically speed up sparse matrix algebra.

He was Program Manager and Architect of the Phoenix Systolic Processor, the first high performance, 280 mega-ops, systolic processor. (1981) With B. R. Rau and C.D. Glaeser, he patented (1981) a fundamental hardware mechanism to improve scheduling VLIW computers. He was Principal Investigator and Architect of TRW's Systolic Adaptive Beamformer, a 350 Megaflop linear algebra processor (1986). This special purpose processor, funded by DARPA/NTO and the Navy, went to sea in an experiment using adaptive beamforming in towed hydrophone arrays.

He was Principal Investigator and Architect of the MOSAIC processor, a ten gigaflop heterogeneous supercomputer developed as part of the DARPA/ISTO Strategic Computing Initiative. (1989) He directed a hardware and software development team to create both a gigabyte per second crossbar switch and the dataflow based CAD system to allow a variety of application specific supercomputers to be rapidly configured.

As Director of Architecture at Plus Logic, Inc. a startup Field Programmable Gate Array company, he defined Plus Logic's next FPGA family including intelligent memory combined with programmable logic (1990).

In 1991 he joined HP Laboratories as Project Manager for Teramac, a trillion operations per second reconfigurable computer. Teramac has been configured to perform DNA sequence matching, volume visualization, and MRI based brain artery detection at 100 times workstation performance. Teramac is the largest defect tolerant processor ever made. Three quarters of the 864 chips in Teramac have defects.

He has patented with W. B. Culbertson (1998) a fundamental method for using a defective machine to find its own defects. In collaboration with Jim Heath and Stan Williams, he has recently developed various architectures for chemically assembled electronic nanocomputers.