© IEEE 2005
Heterogeneous (or asymmetric) chip multiprocessors present
unique opportunities for improving system throughput, reducing
processor power, and mitigating Amdahl’s law. On-chip
heterogeneity allows the processor to better match execution
resources to each application’s needs and to address
a much wider spectrum of system loads — from low to
high thread parallelism — with high efficiency.
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About the authors:
Parthasarathy (Partha) Ranganathan is
a principal research scientist at Hewlett Packard
Labs. His research interests
are in low-power system design, system architecture,
and performance evaluation. Ranganathan received
a PhD in electrical and computer
engineering from Rice University. He is a member
of the IEEE and the ACM.
Norman P. Jouppi is a Fellow at HP Labs. His
research interests include multicore architectures,
memory systems, and cluster interconnects.
Jouppi received a PhD in electrical engineering from
Stanford University. He is a Fellow of the IEEE and
currently serves as chair of ACM SIGARCH.
Rakesh Kumar is a PhD student in the Department of Computer Science
and Engineering at the University of California, San Diego. His
research interests include multicore and multithreaded architectures,
low-power architectures, and on-chip interconnects. Kumar received
a BS in computer science and engineering from the Indian Institute
of Technology, Kharagpur. He is a member of the ACM.
Dean M. Tullsen is an associate professor in the Department of
Computer Science and Engineering at the University of California, San Diego. His research
interests include instruction- and thread-level parallelism and
multithreaded and multicore architectures. Tullsen received a PhD
in computer science and engineering from the University of Washington.
He is a member of the IEEE and the ACM.
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