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Fast Turnaround of a Structured Custom IC Design Using Advanced Design Tools and Methodology
Through the use of several new tools and methodologies, a small team of engineers was able to design and verify a 1.7-million-FET chip in eight months. The tools and methodologies used included a set of guidelines and timing constraints that were met by the customer, a data path compiler, a highly tuned custom multiplier cell that was used in 87 locations, and an automated top-level power connection scheme.
by Rory L. Fisher, Stephen R. Herbener, John R. Morgan, and John R. Pessetto
 Article 17 - apr97a17.pdf
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