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Designing, Simulating, and Testing an Analog Phase-Locked Loop in a Digital Environment
In designing a phase-locked loop for use on several HP ASICs, the digital portion of an existing phase-locked loop was transferred to a behavioral VHDL description and synthesized. A behavioral model was written for the analog section to allow the ASIC designers to run system simulations. A new leakage test was developed that has been very effective in screening out process defects in the filter of the original design.
by Thomas J. Thatcher, Michael M. Oshima, and Cindy Botelho
 Article 14 - apr97a14.pdf
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