|
Physical Design of 0.35-um Gate Arrays for Symmetric Multiprocessing Servers
To meet gate density and system performance requirements for the HP Exemplar S-class and X-class technical servers, a physical design methodology was developed for 1.1-million-raw-basic-cell, 0.35-um CMOS gate arrays. Commercial and ASIC vendor-supplied tools were augmented with internally developed tools to put together a highly optimized physical chip design process.
by Lionel C. Bening, Tony M. Brewer, Harry D. Foster, Jeffrey S. Quigley, Robert A. Sussman, Paul F. Vogel, and Aaron W. Wells
 Article 16 - apr97a16.pdf
This article is available in Adobe Acrobat format (PDF). To view this article you need to have Acrobat Reader 2.0 or later installed on your system. The Acrobat reader is available free of charge in Unix, Dos, Windows and Macintosh formats. You can download the reader from Adobe Systems (www.adobe.com)
|
|
