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Cycle-time Aware Architecture synthesis of Custom Hardware Accelerators
Sivaraman, Mukund; Aditya, Shail
HPL-2002-300
Keyword(s): high-level synthesis; timing analysis; embedded hardware architecture synthesis
Abstract: We present the cycle-time aware architecture synthesis methodology used in PICO-NPA that automatically synthesizes minimal cost RT-level designs from high- level specifications to meet a given cycle-time. This allows subsequent physical synthesis to succeed on first pass with predictable performance. The core of the methodology is a static timing analysis engine that is used at multiple levels - program-level, architecture-level and RT-level - in order to identify, schedule and validate useful operator chains that are incorporated into the design automatically. We present architecture synthesis results for several embedded applications and evaluate the benefits of this technique. Notes: Copyright ACM Published in and Presented at the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems--CASES--8-11 October 2002, Grenoble, France
8 Pages
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