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ShiftQ: A Bufferred Interconnect for Custom Loop Accelerators
Aditya, Shail; Schlansker, Michael S.
HPL-2001-255
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Abstract: ShiftQs are hardware structures consisting of registers and switches which buffer and transport operands among function units within custom hardware loop accelerators. ShiftQs help minimize buffering and interconnect costs by customizing the hardware to the given schedule and by intelligent sharing of register and interconnect resources. This paper describes the ShiftQ schema and a method to automatically synthesize them from modulo-scheduled loops. We also evaluate the cost savings by comparing them against traditional storage and interconnect mechanisms. Notes: Copyright ACM To be published in and presented at CASES '01, November 16-17, 2001, Atlanta, GA
10 Pages
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