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Automatic Architecture Synthesis and Compiler Retargeting for VLIW and EPIC Processors
Aditya, Shail; Rau, B. Ramakrishna
HPL-1999-93
Keyword(s): architecture synthesis; micro-architecture synthesis; VLIW processors; EPIC processors; automatic processor design; abstract architecture specification; datapath design; resource allocation; mdes extraction; compiler retargeting; controlpath design; instruction pipeline design; RTL generation
Abstract: This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing (EPIC) processor architectures starting from an abstract specification of their desired functionality. The process of architecture design makes concrete decisions regarding the number and types of functional units, number of read/write ports on register files, the datapath interconnect, the instruction format, its decoding hardware, and the instruction unit datapath. The processor design is then automatically synthesized into a detailed RTL- level structural model in VHDL along with an estimate of its area. The system also generates the corresponding detailed machine description and instruction format description that can be used to retarget a compiler and an assembler respectively. This process is part of an overall design system, called Program-In-Chip-Out (PICO), which has the ability to perform automatic exploration of the architectural design space while customizing the architecture to a given application and making intelligent, quantitative, cost-performance tradeoffs.
81 Pages
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