Norm Jouppi: Publications

HP Fellow
Director, Exascale Computing Lab
Palo Alto

Selected publications

  1. 11/10: "Simple but Effective Heterogeneous Main Memory with On-chip Memory Controller Support'' by Xiangyu Dong, Naveen Muralimanohar, Yuan Xie, and Norman P. Jouppi, in the proceedings of SC'10, November 2010.
  2. 6/10: "Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores'' by Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, and Norman P. Jouppi, in the Proceedings of the 38th International Symposium on Computer Architecture, St. Malo, June 2010.
  3. 12/09: "An Integrated Power, Area, and Timing Modeling Framework and its Application to Scaling and Clustering Tradeoffs in Future Manycore Architectures" by Sheng Li, Jung Ho Ahn, Richard Strong, Jay Brockman, Dean Tullsen, and Norm Jouppi, in the proceedings of Micro-42, December 2009.
  4. 11/09: "Futute Scaling of Processor-Memory Interfaces" by Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis, Jacob Leverich, and Rob Schreiber, in the proceedings of SC'09, November 2009.
  5. 11/09: "Leveraging 3D PCRAM Technologies to Reduce Checkpoint Overhead for Futute Exascale Systems", by Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, and Yuan Xie, in the proceedings of SC'09, November 2009.
  6. 11/09: "PCRAMsim: A System-Level Phase-Change RAM Simulator", by Xiangyu Dong, Norman P. Jouppi, and Yuan Xie, in the proceedings of ICCAD 09, November 2009.
  7. 10/09: "Resilience Challenges for Exascale Systems", by Norman P. Jouppi, in the proceedings of the 24th International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2009.
  8. 09/09: "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore Processors" by Sheng Li, Jung Ho Ahn, Richard Strong, Jay Brockman, Dean Tullsen, and Norm Jouppi, HP Labs Tech Report HPL-2009-206, September 2009.
  9. 7/09: "A High-Speed Optical Multidrop Bus for Computer Interconnections", by Michael Tan, et. al., IEEE Micro special issue on Hot Interconnects, July 2009.
  10. 7/09: "Introduction to the Special Issue on the 2008 Workshop on the Design, Analysis, and Simulation of Chip Multiprocessors (dasCMP08)" by Norman P. Jouppi, Rakesh Kumar, and Dean Tullsen, ACM SIGARCH Computer Architecture News, July 2009.
  11. 06/09: "Software and Hardware Support for Deterministic Replay of Parallel Programs", by Norman P. Jouppi, Technical Perspective in the Communications of the ACM, June 2009.
  12. 05/09: "CMOS Nanophotonic Switches for Exascale Networks'' by Moray McLaren, Nate Binkert, Jung Ho Ahn, Norm Jouppi, Al Davis, Marco Fiorentino, Rob Schreiber, and Naveen Muralimanohar, (poster) in the proceedings of HP TechCon 2009.
  13. 05-09: "Virtualization for Error Detect and Correct'' by John Byrne, Norman Jouppi, Laura Ramirez, Partha Ranganathan, Bruce Walker, Bob Kessler, and Jim Smullen, (formal presentation) in the proceedings of HP TechCon 2009.
  14. 11/08: "Implementing High Availability Memory with a Duplication Cache" by Nidhi Aggarwal, James E. Smith, Norman P. Jouppi, Kewal K. Saluja, Parthasarathy Ranganathan, in the proceedings of Micro-41, December 2008.
  15. 9/08: "Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs" Jung Ho Ahn, Jacob Leverich, Robert S. Schreiber, and Norman P. Jouppi, IEEE Computer Architecture Letters, September 2008.
  16. 9/08: "A Nanophotonic Interconnect for High-Performance Many-Core Computation", by Ray Beausoleil et. al., 5th IEEE International Conference on Group IV Photonics, September 2008.
  17. 8/08: "A Nanophotonic Interconnect for High-Performance Many-Core Computation", by Ray Beausoleil et. al., Hot Interconnects 16, August 2008.
  18. 8/08: "A High-Speed Optical Multi-drop Bus for Computer Interconnections" by Mike Tan et. al., Hot Interconnects 16, August 2008.
  19. 8/08: "System Implications of Integrated Photonics" by Norman P. Jouppi, in the Proceedings of the International Symposium on Low Power Electronics and Design, Bangalore, August 2008.
  20. 6/08: "A Nanophotonic Interconnect for High-Performance Many-Core Computation" by Ray Beausoleil et. al., cover feature, IEEE LEOS Newsletter, pages 15-22, June 2008.
  21. 6/08: "Corona: System Implications of Emerging Nanophotonic Technology" by Dana Vantrease et. al., in the Proceedings of the 35th International Symposium on Computer Architecture, Beijing, June 2007.
  22. 6/08: "A Comprehensive Memory Modeling Tool and its Application to the Design and Analysis of Future Memory Hierarchies" by Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, and Norman P. Jouppi, in the Proceedings of the 35th International Symposium on Computer Architecture, Beijing, June 2007.
  23. 5/08: "Introduction to the Special Issue on the 2007 Workshop on the Design, Analysis, and Simulation of Chip Multiprocessors (dasCMP07)" by Norman P. Jouppi, Rakesh Kumar, and Dean Tullsen, ACM SIGARCH Computer Architecture News, March 2008.
  24. 5/08: "A Nanophotonic Interconnect for High-Performance Many-Core Computation" by Jung Ho Ahn et. al., in the Proceedings of HP TechCon'08, May 2008.
  25. 5/08: "Optical Buses: Enabling Flexible High-Speed Systems" Mike Tan, Terry Morris, Moray Mclaren, Norm Jouppi, Paul Rosenberg, and Shih-Yuan Wang, in the Proceedings of HP TechCon'08, May 2008.
  26. 4/08: "Reducing Overhead for Soft Error Coverage in High Availability Systems", by Nidhi Aggarwal, Norman P. Jouppi, Partha Ranganathan, James E. Smith, and Kewal Saluja, in the Proceedings of IEEE SELSE-4, April 2008.
  27. 4/08: "CACTI 5.1" by Shyamkumar Thoziyoor, Naveen Muralimanohar, Jung Ho Ahn, and Norman P. Jouppi, HP Tech Report HPL-2008-20.
  28. 1/08: "Architecting Efficient Interconnects for Large Caches with CACTI 6.0" by Naveen Muralimanohar, Rajeev Balasubramonian, and Norman P. Jouppi, in the IEEE Micro Top Picks special issue, January 2008.
  29. 12/07: "Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0" by Naveen Muralimanohar, Rajeev Balasubramonian, and Norman P. Jouppi, in the Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, Chicago, December 2007.
  30. 11/07: "High-performance Ethernet-based Communications for Future Multi-core Processors" by Mike Schlansker et. al. in the Proceedings of IEEE/ACM SC07 (Supercomputing), Reno, November 2007.
  31. 10/07: "CACTI 5.0" by Shyamkumar Thoziyoor, Naveen Muralimanohar, and Norman P. Jouppi, HP Tech Report HPL-2007-167.
  32. 10/07: "Evaluating the Potential of Future On-Chip Clock Distribution using Optical Interconnects" by Nitya Ranganathan and Norman P. Jouppi, HP Tech Report HPL-2007-163.
  33. 6/07: "Benefits from Isolation in Commodity Multicore Processors" by Nidhi Aggarwal, Partha Ranganathan, Norman P. Jouppi, and James E. Smith, in IEEE Computer, June 2007, pp49-59.
  34. 6/07: "Configurable Isolation: Building High-Availability Systems with Commodity Multi-core Processors" by Nidhi Aggarwal, Partha Ranganathan, Norman P. Jouppi, and James E. Smith, in the Proceedings of the 34th International Symposium on Computer Architecture, San Diego, June 2007.
  35. 04/07: "High-Performance Communications with JNIC" by Mike Schlansker, Dick Carter, Jayaram Mudigonda, Nathan Binkert, and Norman P. Jouppi, in the Proceedings of HP TechCon'07, April 2007.
  36. 4/07: "Microprocessors in the Era of Terascale Integration" by Shekhar Borkar, Norman P. Jouppi, and Per Stenstrom, invited "Hot Topic" paper in the Proceedings of Design and Test Europe (DATE), April 2007.
  37. 4/07: "Motivating Commodity Multi-core Processor Design for System-Level Error Protection", by Nidhi Aggarwal, Kewal Saluja, James E. Smith, Partha Ranganathan, Norman P. Jouppi, and George Krejci, in the Proceedings of IEEE SELSE-3, April 2007.
  38. 3/07: "Introduction to the Special Issue on the 2006 Workshop on the Design, Analysis, and Simulation of Chip Multiprocessors (dasCMP06)" by Dean Tullsen, Rakesh Kumar, and Norman P. Jouppi, ACM SIGARCH Computer Architecture News, March 2007.
  39. 12/06: "Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers" by John Sampson, Jean-Francois Collard, Norman P. Jouppi, Brad Calder, and Mike Schlansker, in the Proceedings of Micro-39, December 2006.
  40. 11/06: "The Potential Energy Efficiency of Vector Acceleration" by Christophe Lemuet, John Sampson, Jean-Francois Collard, and Norman P. Jouppi, in the Proceedings of SC06 (Supercomputing), November 2006.
  41. 10/06: "Improving the Performance of Shared Helpers in Chip Multiprocessors", by Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, and Tim Sherwood, in the Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), October 2006.
  42. 9/06: "Core Architecture Optimization for Heterogeneous Chip Multiprocessors" by Rakesh Kumar, Dean Tullsen, and Norman P. Jouppi, in the Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), September 2006.
  43. 6/06: "CACTI 4.0" by David Tarjan, Shyamkumar Thoziyor, and Norman P. Jouppi, HPL Tech Report HPL-2006-86, June 2006.
  44. 05-06: "JNIC - High Performance Interconnects for Scalable Commodity Systems'' by Mike Schlansker, Erwin Oertli, Rob Schreiber, Jeff Collard, and Norm Jouppi, (poster) in the proceedings of HP TechCon 2006.
  45. 12/05: "The Future Evolution of High-Performance Microprocessors" by Norman P. Jouppi, keynote abstract in the proceedings of ACM Micro-38, December 2005.
  46. 12/05: "Fast Synchronization for Chip Multiprocessors" by Jack Sampson, Ruben Gonzalez, Jeff Collard, Norm Jouppi, and Mike Schlansker, in the proceedings of the ACM Workshop on Design, Analysis, and Simulation of Chip Multiprocessors (dasCMP '05), November 2005, published in SIGARCH Computer Architecture News, December 2005.
  47. 12/05: "Dynamically-Configurable Shared CMP Helper Engines for Improved Performance" by Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi, Suleyman Sair, and Tim Sherwood, in the proceedings of the ACM Workshop on Design, Analysis, and Simulation of Chip Multiprocessors (dasCMP '05), November 2005, published in SIGARCH Computer Architecture News, December 2005.
  48. 12/05: "Introduction to the Special Issue on the 2005 Workshop on the Design, Analysis, and Simulation of Chip Multiprocessors (dasCMP05)" by Norman P. Jouppi, Rakesh Kumar, and Dean Tullsen, ACM SIGARCH Computer Architecture News, December 2005.
  49. 11/05: "Heterogeneous Chip Multiprocessors" by Rakesh Kumar, Dean Tullsen, Norman P. Jouppi, and Partha Ranganathan, in IEEE Computer, November 2005.
  50. 6/05: "System-Wide Performance Monitors and Their Application to the Optimization of Coherent Memory Accesses" by Jean-Francois C. Collard, Norman P. Jouppi, and Sami Yehia, in the proceedings of the ACM Principles and Practice of Parallel Programming Conference, June, 2005.
  51. 4/05: "Telepresence Systems with Automatic Preservation of User Head Height, Local Rotation, and Remote Translation" by Norman P. Jouppi and Stan Thomas, in the paper proceedings of the IEEE International Conference on Robotics and Automation, Barcelona, 2005.
  52. 4/05: "Telepresence Systems with Automatic Preservation of User Head Height, Local Rotation, and Remote Translation" by Norman P. Jouppi and Stan Thomas, in the video proceedings of the IEEE International Conference on Robotics and Automation, Barcelona, 2005.
  53. 3/05: "HP MediaLamp" by Rajan Lukose, Joshua Tyler, Stephen Sorkin, Mark Lillibridge, and Erwin Oertli, Proceedings of HP Tech Con 2005.
  54. 2/05: "Enterprise IT Trends and Implications for Architecture Research" by Partha Ranganathan and Norman P. Jouppi, 11th International Symposium on High Performance Computer Architecture, San Francisco, 2005.
  55. 2/05: "System-Wide Performance Monitors" by Jeff Collard and Norman P. Jouppi, in the Workshop on Hardware Performance Monitors, held in conjunction with the 11th International Symposium on High Performance Computer Architecture, San Francisco, 2005.
  56. 12/04: "The Future Evolution of High-Performance Microprocessors" by Norman P. Jouppi, keynote abstract in the proceedings High Performance Computing (HiPC) 2004, Bangalore.
  57. 12/04: "Con-joined Core Chip Multiprocessors" by Rakesh Kumar, Norman P. Jouppi, and Dean Tullsen, in the Proceedings of ACM Micro 2004, Portland, 2004.
  58. 10/04: "BiReality: Mutually-Immersive Telepresence" by Norman P. Jouppi, Subu Iyer, Wayne Mack, Stan Thomas, and April Slayden, in the Proceedings of ACM Multimedia 2004, New York, 2004.
  59. 10/04: "Personal Spatial Radio" by Norman P. Jouppi, and Subu Iyer, in the Proceedings of the 117th Audio Engineering Society Convention, San Francisco, 2004.
  60. 10/04: "A Headphone-free Head-tracked Audio Telepresence System" by Norman P. Jouppi, and Subu Iyer, in the Proceedings of the 117th Audio Engineering Society Convention, San Francisco, 2004.
  61. 6/04: "Region of Interest Editing of MPEG-2 Video Streams in the Compressed Domain" by Jacob Augustine, Shivarama Rao K., Norman P. Jouppi, and Subu Iyer, in the Proceedings of the IEEE International Conference on Multimedia and Expo (ICME), Taipei, 2004.
  62. 6/04: "Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance" by Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, and Keith Farkas, in the Proceedings of the 31st International Symposium on Computer Architecture, Munich, June 2004.
  63. 6/04: "Spatial Audio Conferencing" by Norman P. Jouppi, Subu Iyer, Jacob Augustine, Shivarama Rao K., and Deepa Kuttipparambil, in the Proceedings of HP Tech Con, Orlando, 2004.
  64. 4/04: "A First Generation Surrogate for Mutually-Immersive Mobile Telepresence" a video by Norman P. Jouppi, Wayne Mack, Subu Iyer, Stan Thomas, and April Slayden in the Video Proceedings of IEEE ICRA 2004, New Orleans, April 2004.
  65. 4/04: "A First Generation Mutually-Immersive Mobile Telepresence Surrogate with Automatic Backtracking" by Norman P. Jouppi, Wayne Mack, Subu Iyer, Stan Thomas, and April Slayden in the Proceedings of IEEE ICRA 2004, New Orleans, April 2004.
  66. 3/04: "Steps Towards Mutually-Immersive Mobile Telepresence" a video by Norman P. Jouppi, Wayne Mack, Subu Iyer, Stan Thomas, and April Slayden in the Video Proceedings of IEEE VR 2004, Chicago, March 2004.
  67. 12/03: "Single-ISA Heterogeneous Mult-Core Architectures: The Potential for Processor Power Reduction, by Rakesh Kumar, Keith Farkas, Norman P. Jouppi, Partha Ranganathan, and Dean Tullsen, in the proceedings of ACM Micro-36, December 2003.
  68. 6/03: "A Mult-Core Approach to Addressing the Energy-Complexity Problem in Microprocessors" by Rakesh Kumar, Keith Farkas, Norman P. Jouppi, Partha Ranganathan, and Dean Tullsen, in the proceedings of the 2003 Workshop on Complexity-Effective Design, June 2003.
  69. 4/03: "Processor Power Reduction Via Single-ISA Heterogeneous Mult-Core Architectures" by Rakesh Kumar, Keith Farkas, Norman P. Jouppi, Partha Ranganathan, and Dean Tullsen, in Computer Architecture Letters, Volume 2, April 2003.
  70. 11/02: "First Steps Towards Mutually-Immersive Mobile Telepresence" a video by Norman P. Jouppi, Wayne Mack, Subu Iyer, Stan Thomas, and April Slayden in the Video Proceedings of the ACM Conference on Computer Supported Cooperative Work, New Orleans, November 2002.
  71. 11/02: "First Steps Towards Mutually-Immersive Mobile Telepresence" by Norman P. Jouppi, in the Proceedings of the ACM Conference on Computer Supported Cooperative Work, New Orleans, November 2002.
  72. 10/02: "Mutually-Immersive Audio Telepresence" by Norman P. Jouppi and Michael J. Pan, in the Proceedings of the Audio Engineering Society 113th Convention, Los Angeles, October 2002.
  73. 5/02: "The Optimal Useful Logic Depth Per Pipeline Stage is Approximately 6 FO4" by Hrishikesh Murukkathapoondi, Norman P. Jouppi, Keith Farkas, Premkishore Shivakumar, Doug Burger, and Steven Keckler, in the Proceedings of the 29th International Symposium on Computer Architecture, Anchorage, May 2001.
  74. 8/01: "CACTI 3.0: An Integrated Cache Timing, Power, and Area Model" by Premkishore Shivakumar and Norman P. Jouppi, WRL Technical Report 2001/2, August 2001.
  75. 8/00: "Prefiltered Antialised Lines Using Half-Plane Distance Functions" by Robert McNamara, Joel McCormack, and Norman P. Jouppi, in the Proceedings of the 2000 ACM SIGGRAPH/Eurographics Hardware Workshop, Interlaken, August 2000.
  76. 8/00: "Prefiltered Antialised Lines Using Half-Plane Distance Functions" by Robert McNamara, Joel McCormack, and Norman P. Jouppi, WRL Research Report 98/2, August 2000.
  77. 6/00: Collected slides from ISCA Panel Discussion on "Slow Wires, Hot Chips, and Leaky Transistors: New Challenges in the New Millennium" moderated by Shubu Mukherjee (with contributions from Norman P. Jouppi), from the 27th Annual International Symposium on Computer Architecture, Vancouver, June 2000.
  78. 6/00: "Reconfigurable Caches and Their Application to Media Processing" by Parthasarathy Ranganathan, Sarita V. Adve, and Norman P. Jouppi, in the Proceedings of the 27th Annual International Symposium on Computer Architecture, Vancouver, June 2000.
  79. 2/00: "CACTI 2.0: An Integrated Cache Timing and Power Model" by Glenn Reinman and Norman P. Jouppi, January 2000.
  80. 10/99: "The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning" by Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic, International Journal of Parallel Programming, Special Issue on Micro-30, Volume 27, Number 5, October 1999, pp 327-356.
  81. 10/99: "Simple and Table Feline: Fast Elliptical Lines for Anisotropic Texture Mapping" by Joel McCormack, Keith I. Farkas, Ronald Perry, and Norman P. Jouppi, WRL Research Report 99/1, October 1999.
  82. 9/99: "Readings in Computer Architecture" by Mark Hill, Norman P. Jouppi, and Gurindar Sohi, editors, Morgan Kaufmann, San Francisco, September 1999.
  83. 8/99: "Feline: Fast Eliptical Lines for Anisotropic Texture Mapping" by Joel McCormack, Ronald Perry, Keith I. Farkas, and Norman P. Jouppi, in the Proceedings of ACM SIGGRAPH 99, Los Angeles, August 1999.
  84. 8/99: "Z3: An Economical Hardware Technique for High-Quality Antialiasing and Transparency" by Norman P. Jouppi and Chun-Fa Chang, in the Proceedings of the 1999 ACM SIGGRAPH/Eurographics Hardware Workshop, Los Angeles, August 1999. (Won best paper award).
  85. 7/99: "Neon: A (Big) (Fast) Single-Chip 3D Workstation Graphics Accelerator," by Joel McCormack, Robert McNamara, Christopher Gianos, Larry Seiler, Norman P. Jouppi, Ken Correll, Todd Dutton, and John Zurawski, WRL Research Report 98/1, July 1999.
  86. 5/99: "Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions" by Parthasarathy Ranganathan, Sarita V. Adve, and Norman P. Jouppi, in the Proceedings of the 26th Annual International Symposium on Computer Architecture, Atlanta, May 1999.
  87. 4/99: "Implementing Neon: A 256-bit Graphics Accelerator," by Joel McCormack, Robert McNamara, Christopher Gianos, Larry Seiler, Norman P. Jouppi, Ken Correll, Todd Dutton, and John Zurawski, in the Hot Chips 10 special issue of IEEE Micro, Vol. 19, No. 2, March/April 1999, pp. 58-69.
  88. 4/99: "Real Products, Real Technology: A Guest Editor's Introduction," by Norman P. Jouppi and John Wawrzynek, in the Hot Chips 10 special issue of IEEE Micro, Vol. 19, No. 2, March/April 1999, pp. 10-11.
  89. 9/98: "Neon: A Single-Chip 3D Workstation Graphics Accelerator" by Joel McCormack, Bob McNamara, Chris Gianos, Larry Seiler, Norman P. Jouppi, and Ken Correll. In Proceedings of the 1998 EUROGRAPHICS/SIGGRAPH Workshop on Graphics Hardware, ACM Press, New York, August 1998, pp 123-132. Voted Best Paper/Presentation.
  90. 9/98: "Retrospective on Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers" by Norman P. Jouppi.  In "25 Years of the International Symposium on Computer Architecture: Selected Papers", Guri Sohi editor, p71-73.
  91. 8/98: "Neon: A Big, Fast, 3D Workstation Graphics Accelerator" by Joel McCormack, Bob McNamara, Chris Gianos, Larry Seiler, Norman P. Jouppi, and Ken Correll in the Proceedings of Hot Chips 10, August, 1998.
  92. 7/98: "The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning" by Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic, WRL Research Report 98/8, July 1998.
  93. 12/97: "The Multicluster Architecture: Reducing Cycle Time Through Partitioning" by Keith Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic in the Proceedings of the 30th Annual International Symposium on Microarchitecture, December, 1997.
  94. 6/97: "Memory-System Design Considerations for Dynamically-Scheduled Processors" by Keith Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic, in the Proceedings of the 24st Annual International Symposium on Computer Architecture, Denver, June 1997.
  95. 6/97: "Complexity-Effective Superscalar Processors" by Subbarao Palacharla, Norman P. Jouppi, and James E. Smith, in the Proceedings of the 24st Annual International Symposium on Computer Architecture, Denver, June 1997.
  96. 6/97: "The Relative Importance of Memory Latency, Bandwidth, and Branch Limits to Performance," by Norman P. Jouppi and Parthasarathy Ranganathan, in the 1997 ISCA Workshop on Mixing Logic and DRAM, Denver, June 1997.
  97. 2/97: "Memory-system Design Considerations for Dynamically-scheduled Processors," by Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic, WRL Research Report 97/1, February 1997.
  98. 5/96: "CACTI: An Enhanced Cache Access and Cycle Time Model," by Steven J. E. Wilton and Norman P. Jouppi in the IEEE Journal of Solid-State Circuits, May 1996.
  99. 4/96: "Guest Editor's Introduction: Hot Chips and the Microprocessor," by Norman P. Jouppi and Hasan S. Alkhatib, in the Hot Chips VII special issue of IEEE Micro, April 1996, page 6.
  100. 2/96: "Register File Design Considerations in Dynamically Scheduled Processors," by Keith Farkas, Norman P. Jouppi, and Paul Chow in the Proceedings of the 2nd Conference on High-Performance Computer Architecture, February, 1996.
  101. 1/96: "A Speed, Power, and Supply Noise Evaluation of ECL Driver Circuits," by Norman P. Jouppi, Stefanos Sidiropoulos and Suresh Menon in the IEEE Journal of Solid-State Circuits, January 1996.
  102. 11/95: "Register File Design Considerations in Dynamically Scheduled Processors" by Keith Farkas, Norman P. Jouppi, and Paul Chow, WRL Research Report 95/10, November, 1995.
  103. 1/95: "How Useful are Non-blocking Loads, Stream Buffers, and Speculative Execution in Multiple Issue Processors?" by Keith Farkas, Norman P. Jouppi, and Paul Chow in the Proceedings of the 1st Conference on High-Performance Computer Architecture, January, 1995.
  104. 12/94: "How Useful Are Non-blocking Loads, Stream Buffers, and Speculative Execution in Multiple Issue Processors?," by Keith I. Farkas, Norman P. Jouppi, and Paul Chow, WRL Research Report 94/8, December 1994.
  105. 10/94: "A Fully-Compensated APD Circuit with 10:1 Ratio Between Active and Inactive Current," by Norman P. Jouppi in the Proceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting, October 1994.
  106. 10/94: "A Speed, Power, and Supply Noise Evaluation of ECL Driver Circuits," by Norman P. Jouppi, Stefanos Sidiropoulos and Suresh Menon in the Proceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting, October 1994.
  107. 7/94: "An Enhanced Access and Cycle Time Model for On-Chip Caches," by Norman P. Jouppi and Steven J. E. Wilton, WRL Research Report 93/5, July 1994.
  108. 4/94: "Design, Packaging, and Testing of a 300MHz 115W ECL Microprocessor," by Norman P. Jouppi, Patrick Boyle and John Fitch, in the Hot Chips V special issue of IEEE Micro, April 1994.
  109. 4/94: "Tradeoffs in Two-Level On-Chip Caching," with Steve Wilton in the Proceedings of the 21st Annual International Symposium on Computer Architecture, Chicago, April 1994.
  110. 4/94: "Complexity/Performance Tradeoffs with Non-Blocking Loads," Keith Farkas and Norman P. Jouppi in the Proceedings of the 21st Annual International Symposium on Computer Architecture, Chicago, April 1994.
  111. 3/94: "Complexity/Performance Tradeoffs with Non-Blocking Loads," by Keith I. Farkas and Norman P. Jouppi, WRL Research Report 94/3, March 1994.
  112. 3/94: "Circuit and Process Directions for Low-Voltage Swing Submicron BiCMOS," by Norman P. Jouppi, Suresh Menon, and Stefanos Sidiropoulos, WRL Technical Note TN-45, March 1994.
  113. 11/93: "A 300MHz 115W 32b Bipolar ECL Microprocessor," by Norman P. Jouppi, et. al., in the IEEE Journal of Solid-State Circuits, November 1993.
  114. 11/93: "A 300MHz 115W 32b Bipolar ECL Microprocessor," by Norman P. Jouppi, Patrick Boyle, Jeremy Dion, Mary Jo Doherty, Alan Eustace, Ramsey Haddad, Robert Mayo, Suresh Menon, Louis Monier, Don Stark, Silvio Turrini, Leon Yang, John Fitch, William Hamburgen, Russell Kao, and Richard Swan, WRL Research Report 93/8, November 1993.
  115. 10/93: "Tradeoffs in Two-Level On-Chip Caching," by Norman P. Jouppi and Steven J.E. Wilton, WRL Research Report 93/3, October 1993.
  116. 5/93: "Cache Write Policies and Performance," by Norman P. Jouppi, in the Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, May 1993.
  117. 2/93: "A 300MHz 115W 32b Bipolar ECL Microprocessor with On-chip Caches," by Norman P. Jouppi, et. al., in the Digest of the 1993 International Solid State Circuits Conference, San Francisco, February 1993.
  118. 2/93: "A Pipelined 32b NMOS Microprocessor," Christopher Rowen, Steven Przybylski, Norman P. Jouppi, Thomas Gross, John Shott, and John Hennessy, republished on the 30th anniversary of the International Solid State Circuits Conference in the commemorative supplement, San Francisco, February 1993, pgs 68-69.
  119. 5/92: "A Simulation-Based Study of TLB Performance," J. Bradley Chen, Anita Borg, and Norman P. Jouppi, in the Proceedings of the 19th Annual International Symposium on Computer Architecture, Australia, May 1992.
  120. 5/92: "A Simulation-Based Study of TLB Performance," by J. Bradley Chen, Anita Borg, and Norman P. Jouppi, WRL Research Report 91/2, May 1992.
  121. 12/91: "Cache Write Policies and Performance," by Norman P. Jouppi, WRL Research Report 91/12, December 1991.
  122. 9/91: "Computer Technology and Architecture: An Evolving Interaction," invited paper by John Hennessy and Norman P. Jouppi in the 40th anniversary issue of Computer Magazine, September 1991.
  123. 8/90: "Reducing Compulsory and Capacity Misses," by Norman P. Jouppi, WRL Technical Note TN-53, August 1990.
  124. 6/90: "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," by Norman P. Jouppi, in the Proceedings of the 17th Annual International Symposium on Computer Architecture, Seattle, June 1990. Received award for most influential ISCA paper of 1990 in 2005. Reprinted in "25 Years of the International Symposium on Computer Architecture: Selected Papers", Guri Sohi editor, 1998. Reprinted in "Readings in Computer Architecture", Morgan Kaufmann, 1999.
  125. 6/90: "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," by Norman P. Jouppi, WRL Technical note TN-14, March 1990.
  126. 12/89: "The Non-Uniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance," by Norman P. Jouppi, in the IEEE Transactions on Computers, December 1989.
  127. 10/89: "A 20MIPS Sustained 32b CMOS Microprocessor with High Ratio of Sustained to Peak Performance," by Norman P. Jouppi and Jeff Tang, in the IEEE Journal of Solid-State Circuits, October 1989.
  128. 10/89: "Integration and Packaging Plateaus of Processor Performance," by Norman P. Jouppi, in the Proceedings of the the 1989 International Conference on Computer Design, October 1989.
  129. 7/89: "The Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance," by Norman P. Jouppi, WRL Research Report 89/13, July 1989.
  130. 7/89: "A 20-MIPS Sustained 32-bit CMOS Microprocessor with High Ratio of Sustained to Peak Performance," by Norman P. Jouppi and Jeffrey Y. F. Tang, WRL Research Report 89/11, July 1989.
  131. 7/89: "Integration and Packaging Plateaus of Processor Performance," by Norman P. Jouppi, WRL Research Report 89/10, July 1989.
  132. 7/89: "Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU," by Norman P. Jouppi, WRL Research Report 89/9, July 1989.
  133. 7/89: "A Unified Vector/Scalar Floating-Point Architecture," by Norman P. Jouppi, Jonathan Bertoni, and David W. Wall, WRL Research Report 89/8, July 1989.
  134. 7/89: "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines," by Norman P. Jouppi and David W. Wall, WRL Research Report 89/7, July 1989.
  135. 6/89: "Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU," by Norman P. Jouppi, in the Proceedings of the 16th Annual International Symposium on Computer Architecture, Jerusalem, June 1989.
  136. 4/89: "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines," by Norman P. Jouppi and David Wall, in the Proceedings of the Third Symposium on Architectural Support for Programming Languages and Operating Systems, Boston, April 1989.
  137. 4/89: "A Unified Vector/Scalar Floating-Point Architecture," by Norman P. Jouppi, Jon Bertoni, and David Wall, in the Proceedings of the Third Symposium on Architectural Support for Programming Languages and Operating Systems, Boston, April 1989.
  138. 2/89: "A 20MIPS Sustained 32b CMOS Microprocessor with 64b Data Busses," by Norman P. Jouppi, Jeff Tang, and Jeremy Dion, in the Digest of the 1988 International Solid State Circuits Conference, New York, February 1989.
  139. 6/88: "Superscalar vs. Superpipelined Machines," by Norman P. Jouppi, Computer Architecture News, Vol. 16, No. 3, June 1988.
  140. 4/88: "The MultiTitan: Four Architecture Papers," by Norman P. Jouppi, Jeremy Dion, David Boggs, and Michael J. K. Nielsen, DECWRL tech report 87/8, sole author of CPU and FPU Architecture Papers, April 1988.
  141. 7/87: "Timing Analysis and Performance Improvement of MOS VLSI Designs," by Norman P. Jouppi, IEEE Transactions on CAD, July 1987.
  142. 5/87: "Derivation of Signal Flow Direction in MOS VLSI," by Norman P. Jouppi, IEEE Transactions on CAD, May 1987.
  143. 6/84: "Timing Verification and Performance Improvement of MOS VLSI Designs," Ph.D. Dissertation, Stanford, June 1984.
  144. 6/84: "Timing Verification and Performance Improvement of MOS VLSI Designs," by Norman P. Jouppi, Stanford CSL Technical Report 84-266.
  145. 6/84: "Organization and VLSI Implementation of MIPS," by Steven A. Przybylski, Thomas R. Gross, John L. Hennessy, Norman P. Jouppi, and Chris Rowen, Stanford CSL Technical Report 84-259.
  146. 4/84: "Organization and VLSI Implementation of MIPS," Steven Przybylski, Thomas Gross, John Hennessy, Norman P. Jouppi, and Christopher Rowen, Journal of VLSI Computer Systems, vol. 1, no. 3, Spring 1984; see also Stanford CSL Tech Report 83-259.
  147. 2/84: "A Pipelined 32b NMOS Microprocessor," Christopher Rowen, Steven Przybylski, Norman P. Jouppi, Thomas Gross, John Shott, and John Hennessy, in the Digest of the 1984 International Solid State Circuits Conference, San Francisco, February 1984, pgs 180-181.
  148. 11/83: "Summary of MIPS Instructions," by John Gill, Thomas Gross, John Hennessy, Norman P. Jouppi, Steven Przybylski, and Chris Rowen, Stanford CSL Technical Note 83-237, November 1983.
  149. 6/83: "Timing Analysis for nMOS VLSI," by Norman P. Jouppi, in the Proceeding of the 20th Design Automation Conference, Miami Beach, June 1983, pgs 411-418.
  150. 3/83: "TV: An nMOS Timing Analyzer," by Norman P. Jouppi, in Proceedings of the Third CalTech Conference on VLSI, Pasadena, March 1983, pgs 71-86.
  151. 3/83: "Design of a High Performance VLSI Processor," John Hennessy, Norman P. Jouppi, Steven Przybylski, Christopher Rowen, and Thomas Gross, Stanford CSL Technical Report 83-236.
  152. 3/83: "Design of a High Performance VLSI Processor," John Hennessy, Norman P. Jouppi, Steven Przybylski, Christopher Rowen, and Thomas Gross, invited paper in the Proceedings of the Third CalTech Conference on VLSI, Pasadena, March 1983, pgs 33-54.
  153. 10/82: "MIPS: A Microprocessor Architecture," by John Hennessy, Norman P. Jouppi, Steven Przybylski, Christopher Rowen, Thomas Gross, Forest Baskett, and John Gill, in the Proceedings of the 15th Annual Workshop on Microprogramming, October 1982, pgs 17-22.
  154. 3/82: "Hardware/Software Tradeoffs for Increased Performance," John Hennessy, Norman P. Jouppi, Forest Baskett, Thomas Gross, and John Gill, in the Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, Palo Alto, March 1982, pgs 2-11.
  155. 3/82: "Hardware/Software Tradeoffs for Increased Performance," by John Hennessy, Norman P. Jouppi, Forest Baskett, Thomas Gross, and John Gill, Stanford CSL Technical Report 81-228.
  156. 2/82: "The MIPS Machine," by John Hennessy, Norman P. Jouppi, John Gill, Forest Baskett, Alex Strong, Thomas Gross, Christopher Rowen, and Judson Leonard, in the Proceedings of Spring Compcon, February 1982, pgs 2-7.
  157. 10/81: "MIPS: A VLSI Processor Architecture," John Hennessy, Norman P. Jouppi, Forest Baskett, and John Gill, in Proceedings of the CMU Conference on VLSI Systems and Computations, Pittsburgh, October 1981, pg 337-347.
  158. 10/81: "MIPS: A VLSI Processor Architecture," by John Hennessy, Norman P. Jouppi, Forest Baskett, and John Gill, Stanford CSL Technical Report 81-223.
  159. 6/80: "A Computer Architecture for Natural Language Understanding," Norman P. Jouppi, M.S. Thesis, Northwestern University, June 1980.