Norman P. Jouppi

Biography

Norman P. Jouppi is a fellow and director of the Intelligent Infrastructure Lab at HP Labs, the company’s central research and development arm, overseeing research on building next-generation hardware and software compute infrastructure using a cross-layer inter-disciplinary approach.

Jouppi is well-known for his innovations in computer memory systems, including stream prefetch buffers, victim caching, multi-level exclusive caching and development of the CACTI tool for modeling cache timing, area and power. His research innovations have been adopted in microprocessors from most high-performance microprocessor vendors.

He has also been the principal architect and lead designer of several microprocessors, contributed to the architecture and design of graphics accelerators, and extensively researched video, audio and physical telepresence.

His recent work includes implications of emerging nanophotonic technology on computer systems, low-latency high-bandwidth networking for cluster computing, heterogeneous chip multiprocessor architectures, and blade system architectures.

Jouppi joined HP in 2002 from Compaq Computer Corp., where he was a staff fellow at Compaq’s Western Research Laboratory in Palo Alto, Calif.

From 1984 through 1996, he was a consulting assistant/associate professor in the department of electrical engineering at Stanford University, where he taught classes in VLSI, circuits and computer architecture.

Jouppi received his Ph.D. in electrical engineering from Stanford University in 1984, and a master of science in electrical engineering from Northwestern University in 1980. While at Stanford, he was one of the principal architects and designers of the MIPS microprocessor, as well as a developer of techniques for CMOS VLSI timing verification.

He currently serves as past chair of ACM Special Interest Group on Computer Architecture (SIGARCH), is on the ACM Council and on the Computing Research Association (CRA) board. He is on the editorial board of Communications of the ACM and IEEE Computer Architecture Letters, and is a fellow of the ACM and the IEEE. He holds more than 34 U.S. patents. He has published over 100 technical papers, with several best paper awards and one Symposium on Computer Architecture (ISCA) Influential Paper Award.

Research interests

Computer memory systems; microprocessor architecture and design; video, audio and physical telepresence; low-latency high-bandwidth networking for cluster computing; heterogeneous chip multiprocessor architectures, and blade system architectures.

Publications

• He has published over 100 technical papers, with several best paper awards and one Symposium on Computer Architecture (ISCA) Influential Paper Award. » view publications

   

Awards

HP Senior Fellow

HP Fellows are pioneers in their fields, setting the standards for technical excellence and driving the direction of research in their respective disciplines.

IEEE Fellow

For contributions to the design and analysis of high-performance processors and memory systems. (2003)

ACM Fellow

For contributions to the design and analysis of high-performance processors and memory systems. (2006)

Professional Activities

• Past chair of ACM Special Interest Group on Computer Archictecture (SIGARCH)
• ACM Council and on the Computing Research Association (CRA) board
• Editorial board of Communications of the ACM and IEEE Computer Architecture Letters

Patents

Norm holds more than 35 U.S. patents. » view patents