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Clock Design and Measurement Issues in Pentium(TM) Systems
Design difficulties in producing a statistically stable 66-MHz Pentium system are reviewed. The information is pertinent to many other new, high-speed processors as well. A new, more informed approach to designing well-timed systems in this performance class is proposed. Measurements that support this approach are examined, particularly those made with the HP 8133A pulse generator.
by Michael K. Williams and Andreas M.R. Pfaff
 Article 9 - dec94a9.pdf
Tolerance Mechanisms in Clock Distribution Networks - dec94a9a.pdf
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