HP Labs Technical Reports

A Scaling Scheme for Interconnect in Deep-Submicron Processes

Rahmat, Khalid; Nakagawa, Sam; Oh, Soo-Young; Moll, John

HPL-95-77

Keyword(s):

Abstract: In this paper, we study the requirements for interconnect in deep-submicron technologies and identify critical factors that will require innovations in process technology, process integration and circuit-and-systems design techniques. We have used realistic parameters for transistors, interconnect and system performance for the future technology generations to show that delay and cross talk will be severe constraints for global lines. To meet these limits a reverse scaling scheme is proposed, which includes the impact of new materials, for optimally designing global interconnect for a given application domain such as microprocessors, ASIC's or memory. For local interconnect, cross-talk is the major challenge which can be addressed by selectively using larger drivers to reduce cross-talk noise when necessary.

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