HP Labs Technical Reports
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HPL-PD Architecture Specification: Version 1.0
Kathail, Vinod; Schlansker, Michael; Rau, B. Ramakrishna
HPL-93-80R1
Keyword(s): Instruction-level parallelism; parametric architecture; EPIC; VLIW; superscalar; speculative execution; predicated execution; programmatic cache control; run-time memory disambiguation; branch architecture
Abstract: HPL-PD is a parametric processor architecture conceived for research in instruction-level parallelism (ILP). Its main purpose is to serve as a vehicle to investigate processor architectures having significant parallelism and to investigate the compiler technology needed to effectively exploit such architectures. The architecture is parametric in that it admits machines of different composition and scale, especially with respect to the nature and amount of parallelism offered. The architecture admits EPIC, VLIW and superscalar implementations so as to provide a basis for understanding the merits and demerits of these different styles of implementation. This report describes those parts of the architecture that are common to all machines in the family. It introduces the basic concepts such as the structure of an instruction, instruction execution semantics, the types of register files, etc. and describes the semantics of the operation repertoire.
58 Pages
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