Technical Reports
HPL-2011-65
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Performance Impacts of Non-blocking Caches in Out-of- order Processors
Li, Sheng; Chen, Ke; Brockman, Jay B.; Jouppi, Norman P.
HP Laboratories
HPL-2011-65
Keyword(s): Non-blocking cache; MSHR; Out-of-order Processors
Abstract: Non-blocking caches are an effective technique for tolerating cache-miss latency. They can reduce miss- induced processor stalls by buffering the misses and continuing to serve other independent access requests. Previous research on the complexity and performance of non-blocking caches supporting non-blocking loads showed they could achieve significant performance gains in comparison to blocking caches. However, those experiments were performed with benchmarks that are now over a decade old. Furthermore the processor that was simulated was a single-issue processor with unlimited run-ahead capability, a perfect branch predictor, fixed 16-cycle memory latency, single-cycle latency for floating point operations, and write- through and write-no-allocate caches. These assumptions are very different from today's high performance out-of-order processors such as the Intel Nehalem. Thus, it is time to re-evaluate the performance impact of non-blocking caches on practical out-of-order processors using up-to-date benchmarks. In this study, we evaluate the impacts of non-blocking data caches using the latest SPECCPU2006 benchmark suite on practical high performance out-of-order (OOO) processors. Simulations show that a data cache that supports hit-under-2-misses can provide a 17.76% performance gain for a typical high performance OOO processor running the SPECCPU 2006 benchmarks in comparison to a similar machine with a blocking cache.
9 Pages
External Posting Date: July 6, 2011 [Fulltext]. Approved for External Publication
Internal Posting Date: July 6, 2011 [Fulltext]