Technical Reports
HPL-2009-85
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CACTI 6.0: A Tool to Model Large Caches
Muralimanohar, Naveen; Balasubramonian, Rajeev; Jouppi, Norman P.
HP Laboratories
HPL-2009-85
Keyword(s): No keywords available.
Abstract: Future processors will likely have large on-chip caches with a possibility of dedicating an entire die for on-chip storage in a 3D stacked design. With the ever growing disparity between transistor and wire delay, the properties of such large caches will primarily depend on the characteristics of the interconnection networks that connect various sub- modules of a cache. CACTI 6.0 is a significantly enhanced version of the tool that primarily focuses on interconnect design for large caches. In addition to strengthening the existing analytical model of the tool for dominant cache components, CACTI 6.0 includes two major extensions over earlier versions: first, the ability to model Non-Uniform Cache Access (NUCA), and second, the ability to model different types of wires, such as RC based wires with different power, delay, and area characteristics and differential low-swing buses. This report details the analytical model assumed for the newly added modules along with their validation analysis.
24 Pages
Additional Publication Information: Published in International Symposium on Microarchitecture, Chicago, Dec 2007.
External Posting Date: April 21, 2009 [Fulltext]. Approved for External Publication
Internal Posting Date: April 21, 2009 [Fulltext]