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ACRES Architecture and Compilation
Ang, Boon Seong; Schlansker, Michael
HPL-2003-209R1
Keyword(s): reconfigurable computing; spatial compilation; pipelined interconnect; distributed control; remote branch architecture; reconfigurable memory
Abstract: High-performance computing engines often provide product-defining functionality within consumer devices. These devices are traditionally implemented using either ASICs or embedded processors. ASICS are inflexible and require high design cost while embedded processors provide inadequate compute power and efficiency for specialized applications. This work describes the ACRES (Architecture and Compiler for REconfigurable Systems) platform that combines the flexibility of a programmable technology and the efficiency of custom hardware without incurring high- cost, high-risk chip development. The ACRES platform consists of a programmable computing fabric architecture and an associated spatial compiler. A spatial compilation procedure ties together novel configurable elements including interconnect, memory and distributed control. A key compilation feature is early spatial planning that influences subsequent architectural decisions. Operation scheduling follows and uses accurate latency information to generate efficient execution schedules. This paper describes the motivating assumptions, key ideas and technologies advocated in the ACRES platform. Implementation and evaluation is the topic of future work.
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