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MPOC: A Chip Multiprocessor for Embedded Systems
Richardson, Stephen
HPL-2002-186
Keyword(s): CMP; chip multiprocessor; embedded processor; embedded DRAM; CPACM
Abstract: MPOC was an ambitious microprocessor project undertaken at Hewlett Packard's Palo Alto Research Lab from about 1998 until early in the year 2001. MPOC was designed to be a single-chip community of identical high-speed RISC processors surrounding a large common storage area. Each processor would have its own clock, cache and program counter. Each processor was to be small and simple, such that it would run very fast using minimal power requirements. MPOC attempted to break new ground in several categories, including 1) novel funding for microprocessor research; 2) introducing multiprocessing to the embedded market; 3) trading design complexity for coarse grain parallelism; 4) a novel four-stage microprocessor pipeline; and 5) using co-resident on-chip DRAM to supply chip multiprocessor memory needs. MPOC's first generation design targeted the embedded printer market. Using TSMC's 0.18 micron CMOS process including combined logic and DRAM, it planned to place four processors on a single chip. Each processor would be 1.5 x 2 mm, including a 4KB instruction cache and a 4KB data cache. The processors shared a single on-chip 4MB DRAM occupying about 4 x 8 mm, designed to fill a 32B cache line in 20 ns across a 256b internal bus. Total chip size would be approximately 55 sq mm with a target sell price of $40 to $50. An alternative 0.13 micron part could put 4 CPU's and 12 MB of DRAM on a 59 sq mm chip.
13 Pages
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