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PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
Schreiber, Robert; Aditya, Shail; Mahlke, Scott; Kathail, Vinod; Rau, B. Ramakrishna; Cronquist, Darren; Sivaraman, Mukund
HPL-2001-249
Keyword(s): high-level synthesis; ASIC; systolic array
Abstract: The PICO-NPA system automatically synthesizes nonprogrammable accelerators (NPAs) to be used as co- processors for functions expressed as loop nests in C. The NPAs it generates consist of a synchronous array of one or more customized processor datapaths, their controller, local memory, and interfaces. The user, or a design space exploration tool that is a part of the full PICO system, identifies within the application a loop nest to be implemented as an NPA, and indicates the performance required of the NPA by specifying the number of processors and the number of machine cycles that each processor uses per iteration of the inner loop. PICO-NPA emits synthesizable HDL that defines the accelerator at the register transfer level (RTL). The system also modifies the user's application software to make use of the generated accelerator. The main objective of PICO-NPA is to reduce design cost and time, without significantly reducing design quality. Design of an NPA and its support software typically requires one or two weeks using PICO-NPA which is a many-fold improvement over the industry norm. In addition, PICO-NPA can readily generate a wide-range of implementations with scalable performance from a single specification. In experimental comparison of NPAs of equivalent throughput, PICO-NPA designs are slightly more costly than hand-designed accelerators. Logic synthesis and place-and-route have been performed successfully on PICO-NPA designs, which have achieved high clock rates. Notes: To be published in the Journal of VLSI Signal Processing
23 Pages
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