| |
Click here for full text:
Design of a Synthesisable Reed-Solomon ECC Core
Banks, David
HPL-2001-124
Keyword(s): Reed-Solomon; error correction; verilog; synthesis; synthesisable; hardware; ECC; Galois field
Abstract: In this report we describe the design of a Reed-Solomon error correction core that supports errors and erasures decoding. In a second report HPL-2001-125 we describe the verification of this core. The core consists of separate encoder and decoder blocks that can be operated independently, each with symbol wide data paths. These blocks have sufficient throughput to handle back-to-back codewords, and the overall latency is typically less than two codewords. The design is expressed in the Verilog hardware description language (Verilog HDL), and is fully synthesisable. The design supports a wide range of different Reed-Solomon codes, with the choice of a particular code being made at synthesis time. This approach has a number of advantages that aid shorter product design cycles, by allowing the changes in the choice of code and target technology to be made late in the design cycle. Because of its flexibility, the design could be reused across a wide range of products with differing coding requirements. A sample design configured for a RS(160,128,T=16) code in GF(2^8) was targeted to the Agere HL200CDE 0.20um standard cell library. This resulted in a gate count of 72K gates, an encoder latency of 2 cycles and a decoder latency of 305 cycles. The design could be clocked at 70MHz.
53 Pages
Back to Index
|
printable version
