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TITLE: Error Correction Coding for Flash Memories
SPEAKER: Eitan Yaakobi (UC San Diego)
DATE: 10:00 - 11:00 AM, Friday, August 14, 2009
LOCATION: Sigma, 1L
ABSTRACT:
Non-volatile, solid-state NAND-flash memory devices are finding use in
an increasing number of computing and consumer electronic
devices. They have replaced hard drives in many of these applications
because of their high data-transfer rates, mechanical durability, and
low power consumption. To date, flash memory devices have used only
low-redundancy ECC codes with minimal error correction and detection
capabilities, such as single bit-error correcting Hamming codes and
basic error-detecting cyclic redundancy check (CRC) codes. The demand
for increased storage capacity, coupled with the introduction of
multilevel cell (MLC) flash technology, has created the need for more
powerful ECC methods, such as BCH codes and Reed-Solomon (RS)
codes.
In this work, we use an extensive empirical database of errors induced
by write, read, and erase operations to develop a comprehensive
understanding of the error mechanisms and error characteristics of
flash memories. We also use the error measurements to compare the
performance of BCH and RS codes over a range of redundancies and
error-correction capabilities when applied at the page level. In
addition, we examine the effectiveness of interleaving techniques and
burst-error correcting codes, as well as asymmetric-error correcting
schemes that can improve performance if there is a bias in the
direction of errors (i.e., from '0' to '1' or from '1' to '0'). The
potential benefit of coding across multiple pages within a block is
also investigated. One of the distinctive properties of flash memory
is its read-write asymmetry. That is, reading an individual page is
easily implemented, whereas rewriting a previously stored page
requires the erasure of the entire block containing the page, followed
by the rewriting of the entire contents of the block, including the
updated page. This erase-rewrite operation incurs a substantial cost
in time and power consumption. Moreover, flash memory performance is
degraded by repeated block erasures, thereby limiting the lifetime of
the device. Nowadays, it is of high interest to design codes allowing
information to be written multiple times before erasing the memory. We
will survey some of the recent results related to this topic and
discuss them from the practical and theoretical points of view.
BIOGRAPHY:
Eitan Yaakobi received the B.A. and M.Sc. degrees from the Technion -
Israel Institute of Technology, Haifa, Israel, in 2005 and 2007
respectively, from the Computer Science Department. He is currently a
Ph.D. candidate in Electrical and Computer Engineering at the
University of California, San Diego, where he is associated with the
Center for Magnetic Recording Research. His advisors are Prof. Paul
Siegel, Prof. Alexander Vardy, and Prof. Jack Wolf. His research
interests include algebraic error-correction coding, coding theory,
and their applications for digital data storage, and in particular for
flash memories.
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