Development and Use of Electronic Schematic Capture in the Specification and Simulation of a Structured-Custom ASIC

ASIC designers must sometimes provide the ASIC vendor with documentation describing the data path of the chip and its relationship to the control portion. This paper describes a method and attendant tools that facilitate the employment of commonly available electronic schematic capture software to ensure that the documentation given to the ASIC vendor always matches the Verilog HDL descriptions used by the ASIC designers for simulation.

by David A. Burgoon