HP Labs Technical Reports

A Scaling Scheme for Interconnect in Deep-Submicron Processes

Rahmat, Khalid; Nakagawa, Osamu; Oh, Soo-Young; Moll, John; Lynch, William T.

HPL-95-123

Keyword(s):

Abstract: In this paper, we study the requirements for interconnect in deep-submicron technologies and identify critical factors that will require innovations in process technology, process integration and circuit-and-system design techniques. We also propose a scaling scheme for global lines to optimize the interconnect for a given application domain such as microprocessors, ASIC's or memory. For local interconnect we demonstrate that cross-talk in the major challenge which can be addressed by selectively using larger drivers to reduce cross-talk noise when necessary.

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