Naveen Muralimanohar

Biography

Naveen Muralimanohar is a researcher at Hewlett Packard Labs. His research interests include designing and modeling next generation memory system, building communication fabrics for future servers and data centers, and solving reliability challenges associated with large compute clusters.

 

Research interests

• Memory architecture 
• CACTI  - Cache/Memory modeling tool 
• Interconnect design

Awards

• Best paper award for 'Non-Uniform Power Access for Large Caches with Low-Swing Wires' at the 16th International Conference on High Performance Computing (2009).
• Research on large cache modeling appeared in IEEE Micro's Special Issue on Top Picks from 2007 Computer Architecture Conferences. 
• HP Labs scholarship 2007-2008 
• School of Computing Fellowship 2005-2006
• Intel KUDOS Award (2006) for my work on ASIM simulator and fixing a critical bug that improved the performance of the simulator by 22x
• Outstanding mathematics student award (1997)

Publications

Book:

• Multi-Core Cache Hierarchies, Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar, Morgan and Claypool Publishers, 2011.

Book Chapters: 

• Naveen Muralimanohar, Jung Ho Ahn, Norm Jouppi, 'Memory Modeling with CACTI' to appear in the book titled 'Processor and System-on-Chip Simulation', Publisher-Springer 2010 

• Ahn et al., 'CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study' to appear in the book titled 'Low Power NoCs', Publisher-Springer 2010

Conference & Journal Papers:     

• The Role of Optics in Future High Radix Switch Design, Nathan Binkert, Al Davis, Norm Jouppi, Moray McLaren, Naveen Muralimanohar, Jung Ho Ahn, 38th International Symposium on Computer Architecture (ISCA-38), San Jose, June 2011 
• Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems, Aniruddha N Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norm Jouppi, 38th International Symposium on Computer Architecture (ISCA-38), San Jose, June 2011 
• FREE-p: Protecting Non-Volatile Memory Against Both Hard and Soft Errors, Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Partha Ranganathan, Norm Jouppi, Mattan Erez, 17th International Symposium on High Performance Computer Architecture (HPCA-17), San Antonio, February 2011   
• Simple but Effective Heterogeneous Main Memory with On-chip Memory Controller Support, Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norm Jouppi, 23rd Conference on Supercomputing (SC-23), New Orleans, November 2010
• Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores, Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, and Norm Jouppi, 37 International Symposium on Computer Architecture (ISCA-37), St. Malo, June 2010   
• Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks, Aniruddha N. Udipi, Naveen Muralimanohar, and Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16), Bangalore, January 2010
• Non-Uniform Power Access in Large Caches with Low-Swing Wires, Aniruddha N. Udipi, Naveen Muralimanohar, and Rajeev Balasubramonian, 16th International Conference on High-Performance Computing (HiPC-16), Kochi, December 2009 (Best Paper Award) 
• Leveraging 3D PCRAM Technologies to Reduce Checkpoint Overhead in Future Exascale Systems, Xiangyu Dong, Naveen Muralimanohar, Norm Jouppi, Richard Kaufmann, and Yuan Xie, 22nd Conference on Supercomputing (SC-22), Oregon, November 2009 
• Optimizing Communication and Locality in a 3D Stacked Reconfigurable Cache Hierarchy, Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishanker Iyer, Srihari Makineni, and Donald Newell, 15th International Conference on High-Performance Computer Architecture (HPCA-15), North Carolina, February 2009 
• Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory, Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, and Rajeev Balasubramonian, 7th International Conference on Parallel Architectures and Compilation Techniques (PACT-7), Toronto, October 2008 
• Architecting Efficient Interconnects for Large Caches with CACTI 6.0, Naveen Muralimanohar, Rajeev Balasubramonian, and Norm Jouppi, IEEE Micro's Special issue on Top Picks, Jan/Feb 2008 
• Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0, Naveen Muralimanohar, Rajeev Balasubramonian, and Norm Jouppi, 40th International Symposium on Microarchitecture (MICRO-40), Chicago, December 2007 
• Interconnect Design Considerations for Large NUCA Caches, Naveen Muralimanohar and Rajeev Balasubramonian, 34th International Symposium on Computer Architecture (ISCA-34), San Diego, June 2007 
• The Effect of Interconnect Design on the Performance of Large L2 Caches, Naveen Muralimanohar and Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2), Yorktown Heights, October 2006  
• Leveraging Wire Properties at the Microarchitectural Level, Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and  John Carter, IEEE Micro, Vol. 26, No. 6, Nov/Dec 2006
• Interconnect-Aware Coherence Protocols for Chip Multiprocessors, Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, International Symposium on Computer Architecture (ISCA-33), Boston, June 2006 
• Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, March 2006  
• Microarchitectural Wire Management for Performance and Power in Partitioned Architectures, Rajeev Balasubramonian, Naveen Muralimanohar, Karthikr Ramani, and Venkatanand Venkatachalapathy, 11th International Symposium on High-Performance Computer Architecture (HPCA-11), San Francisco, February 2005 

Workshop Papers

• A Case Study of Incremental and Background Hybrid In-Memory Checkpointing, Xiangyu Dong, Naveen Muralimanohar, Norman Jouppi, and Yuan Xie, Workshop on Exascale Evaluation and Research Techniques, held in conjunction with ASPLOS-15, Pittsburgh, March 2010 
• Wire Management for Coherence Traffic in Chip Multiprocessors, Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 6th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-32, Madison, June 2005 
• Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors, Karthik Ramani, Naveen Muralimanohar, and Rajeev Balasubramonian, 5th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-31, Munich, June 2004 

Downloads

isca11a - ocm.pdf (492.69 KB) - isca11ocm
isca11b - hrs.pdf (923.15 KB) - isca11hrs
hpca11.pdf (353.38 KB) - hpca11freep
taco11.pdf (3.24 MB) - taco
sc10.pdf (272.55 KB) - sc10
isca10.pdf (690.55 KB) - SSA
exert10.pdf (358.7 KB) - Checkpointing
sc09.pdf (1.1 MB) - 3D checkpointing
hpca10.pdf (1.51 MB) - Scalable Bus
hipc09.pdf (341.67 KB) - hipc
hpca09.pdf (464.17 KB) - 3D Reconfigurable Caches
pact08.pdf (181.13 KB) - Scalable TM
toppicks08.pdf (693.33 KB) - Top picks
micro07.pdf (485.4 KB) - micro07
isca07.pdf (278.36 KB) - isca07
ieeemicro06.pdf (168.28 KB) - ieeemicro
pac206.pdf (197.64 KB) - NUCA
ispass06.pdf (219.36 KB) - ispass06
isca06.pdf (157.97 KB) - isca06
hpca05.pdf (135.31 KB) - hpca05
wced05.pdf (89.43 KB) - wced05
wced04.pdf (162.92 KB) - wced04