HP Labs Technical Reports

The Implementation and Evaluation of a Compiler- Directed Memory Interface

McCarthy, Dominic; Quick, Stuart

HPL-97-145

Keyword(s): computer architecture; memory hierarchy; caches; DRAM; burst buffer; compiler; SUIF; performance; low cost

Abstract: This paper describes a novel memory interface architecture, called burst buffers. Although simple, it regularly attains more than a factor of two improvement in performance for media algorithms above a normal data cache using conventional DRAM technology. This paper shows that exposing the features of main memory permits architectural and compiler innovations. Performance gains are achieved by improving the use of available bandwidth from DRAM by utilising three techniques: long bursts, burst pipelining and buffer re-use. This paper demonstrates the benefits of the new memory interface architecture when included in an embedded system alongside the data cache. This interface adds little or no extra system cost.

22 Pages

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