Technical Reports
HPL-2009-326
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Power Management of Datacenter Workloads Using Per- Core Power Gating
Leverich, Jacob; Monchiero, Matteo; Talwar, Vanish; Ranganathan, Partha; Kozyrakis, Christos
HP Laboratories
HPL-2009-326
Keyword(s): power, multicore, datacenter, architecture
Abstract: While modern processors offer a wide spectrum of software-controlled power modes, most datacenters only rely on Dynamic Voltage and Frequency Scaling (DVFS, a.k.a. P-states) to achieve energy efficiency. This paper argues that, in the case of datacenter workloads, DVFS is not the only option for processor power management. We make the case for per-core power gating (PCPG) as an additional power management knob for multi-core processors. PCPG is the ability to cut the voltage supply to selected cores, thus reducing to almost zero the leakage power for the gated cores. Using a testbed based on a commercial 4-core chip and a set of real-world application traces from enterprise environments, we have evaluated the potential of PCPG. We show that PCPG can significantly reduce a processor's energy consumption (up to 40%) without significant performance overheads. When compared to DVFS, PCPG is highly effective saving up to 30% more energy than DVFS. When DVFS and PCPG operate together they can save up to almost 60%.
4 Pages
Additional Publication Information: Published in Computer Architecture Letter (IEEE Computer Society)
External Posting Date: September 21, 2009 [Fulltext]. Approved for External Publication
Internal Posting Date: September 21, 2009 [Fulltext]