Technical Reports
HPL-2009-180
Click here for full text:
Future Scaling of Processor-Memory Interfaces
Ahn, Jung Ho; Jouppi, Norman P.; Schreiber, Robert S.
HP Laboratories
HPL-2009-180
Keyword(s): DRAM, memory system, rank subsetting, Multicore DIMM, mini-rank, ECC, chipkill
Abstract: Continuous evolution in process technology brings energy efficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high bandwidth and capacity, global wires improve slowly, and more cells are susceptible to hard and soft errors. Recently, there are proposals aiming at better main-memory energy efficiency by dividing a memory rank into subsets. We holistically assess the effectiveness of rank subsetting in the context of system-wide performance, energy-efficiency, and reliability perspectives. We identify the impact of rank subsetting on memory power and processor performance analytically, then verify the analyses by simulating a chip-multiprocessor system using multithreaded and consolidated workloads. We extend the design of Multicore DIMM, one proposal embodying rank subsetting, for high-reliability systems and show that compared with conventional chipkill approaches, it can lead to much higher system-level energy efficiency and performance at the cost of additional DRAM devices.
12 Pages
Additional Publication Information: To be presented at SC09, the International Conference for High Performance Computing, Networking, Storage and Analysis, November 14-20, 2009 at Portland, Oregon
External Posting Date: August 6, 2009 [Fulltext]. Approved for External Publication
Internal Posting Date: August 6, 2009 [Fulltext]