Code Size Minimization and Retargetable Assembly for Custom EPIC and VLIW Instruction Formats

Aditya, Shail; Mahlke, Scott A.; Rau, B. Ramakrishna

HPL-2000-141

Keyword(s): EPIC; VLIW; instruction format design; code size minimization; noop compression; design automation; custom templates; retargetable assembly

Abstract: PICO is a fully automated system for designing the architecture and the microarchitecture of VLIW and EPIC processors. A serious concern with this class of processors, due to their very long instructions, is their code size. One focus of this paper is to describe a series of code size minimization techniques used within PICO, some of which are applied during the automatic design of the instruction format, while others are applied during program assembly. The design of a retargetable assembler to support these techniques also poses certain novel challenges which constitute the second focus of this paper. Contrary to widely held perceptions, we demonstrate that it is entirely possible to design VLIW and EPIC processor that are capable of issuing large numbers of operations per cycle, but whose code size is only moderately larger than that for a sequential CISC processor.

31 Pages

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