Jianhua (Joshua) Yang

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Senior Researcher
Palo Alto

Biography

R&D Engineer
Huawei Technologies
2000 - 2001

Education:
University of Wisconsin - Madison
Ph. D , Materials Science Program
Thesis: Engineering and Characterizing Nanoscale Multilayers for Magnetic Tunnel Junctions

University of Wisconsin - Madison
Matster, Materials Science Program

Southeast University, Nanjing, China
B.S. , Materials processing Engineering

Authored and co-authored over 50 papers in academic journals, over 50 papers in international technical conferences and holding 4 granted and over 60 pending US Patents.

 

Research interests

Nanoelectronics, Nanoionics, Nanothermodynamics especailly for non-volatile memory technologies: fabrications, characterizations and applications.

Awards

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Publications

Selected recent papers:

Patents

4

Professional activities

Co-Editor:
Applied Phyisc A This is a Non-HP site


Book/Journal issue (Ed.):

  • 'Non-volatile memory based on  nanostructures This is a Non-HP site', 2011, NANOTECHNOLOGY This is a Non-HP site
  • 'Special Issue on memristive and resistive devices and systems This is a Non-HP site', 2011, APPLIED PHYSICS A This is a Non-HP site  

    • Book chapter:
    'Oxide based memristive nanodevices' in book 'Emerging Nonvolatile Memories', in press

    Program/technical committees:

  • The International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS);
  • 11th Non-Volatile Memory Technology Symposium (NVMTS 2011)

    Journal referees:
    Adv Mater, Adv Funct Mater, Nano Lett, ACS Nano, APL, JAP, IEEE Nano, IEEE ED, IEDL, ESL, Chem Mater, JEM, J. Phys. D etc.

    Recent invited talks:
  • International Conference on Communications, Circuits and Systems (ICCCAS 2009) San Jose, California.
  • Seminar, 2009, University of California, Santa Cruz, California.
  • The 7th International Conference on Advanced Materials and Devices (ICAMD 2009), Jeju island, Korea.
  • Seminar, 2009, Seoul National University, Korea.
  • Invited Lecture, May/2009, UCSC-NASA Ames Research Center,California.
  • The 10th Non-volatile memory technology symposium (NVMTS 2009), Portland, Oregon.
  • International Symposium on Integrated Functionalities ( ISIF 2010), San Juan, Puerto Rico.
  • Advances in nonvolatile memory materials and devices (2010), Suzhou, China.
  • Seminar, 2010, Peking University, Beijing, China.
  • Seminar, 2010, Chinese Academy of Science, Beijing, China.
  • International Symposium on Materials for Enabling Nanodevices (ISMEN 2010), UCLA, California.
  • seminar, 2011, IEEE Computer Society, San Jose California.
  • The Frontier of Functional-Oxide Nano Electronics workshop, 2011, Tsukuba, Japan.
  • Seminar, 2011, IEEE Electronic Device Society, Santa Clara, California.
  • The 11th Non-volatile memory technology symposium (NVMTS 2011), Shanghai, China (Keynote).

    • Interview articles:

  • Memristors: ready for prime time from EE Times (magazine) 
  • Using the Memristor: Assessing the future for electronics - newest circuit element from Electronic Products (magazine)
  • Engineering memristor: Control over device could pave way for computers that learn from Nanotechnology Now (Website)